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IRFD110
Data Sheet July 1999 File Number
2314.3
1A, 100V, 0.600 Ohm, N-Channel Power MOSFET
This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17441.
Features
* 1A, 100V * rDS(ON) = 0.600 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER IRFD110 PACKAGE HEXDIP BRAND IRFD110
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
HEXDIP
DRAIN GATE SOURCE
4-269
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
IRFD110
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified IRFD110 100 100 1.0 8.0 20 1.0 0.008 19 -55 to 150 300 260 UNITS V V A A V W W/oC mJ oC
oC oC
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 9) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC MIN 100 2.0 1.0 0.8 VGS = 10V, ID 1.0A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figure 13) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1MHz (Figure 10) Measured from the Drain Lead, 2mm (0.08in) from Package to Center of Die Measured from the Source Lead, 2mm (0.08in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device's Inductances
D LD G LS S
TYP 0.5 1.2 10 15 15 10 5.0 2.0 3.0 135 80 20 4.0
MAX 4.0 25 250 100 0.6 20 25 25 20 7.0 -
UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance
ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD
VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V ID = 0.8A, VGS = 10V (Figures 7, 8) VDS > ID(ON) x rDS(ON)MAX , ID = 0.8A (Figure 11) VDD = 0.5 x Rated BVDSS, ID 1.0A, RG = 9.1, RL = 50 MOSFET Switching Times are Essentially Independent of Operating Temperature
-
Internal Source Inductance
LS
-
6.0
-
nH
Thermal Resistance Junction to Ambient
RJA
Free Air Operation
-
-
120
oC/W
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IRFD110
Source to Drain Diode Specifications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 4) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D
MIN -
TYP -
MAX 1.0 8.0
UNITS A A
S
Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES:
VSD trr QRR
TJ = 25oC, ISD = 1.0A, VGS = 0V (Figure 12) TJ = 150oC, ISD = 1.0A, dISD/dt = 100A/s TJ = 150oC, ISD = 1.0A, dISD/dt = 100A/s
-
100 0.2
2.5 -
V ns C
2. Pulse test: pulse width 300s, duty cycle 2%. 3. VDD = 25V, starting TJ = 25oC, L = 28.5mH, RG = 25, peak IAS = 1.0A. 4. Repetitive rating: pulse width limited by maximum junction temperature.
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8
Unless Otherwise Specified
1.0
ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150
0.8
0.6
0.6 0.4
0.4
0.2 0
0.2
0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
5 VGS = 10V VGS = 9V VGS = 8V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 7V 3 VGS = 6V 2
ID , DRAIN CURRENT (A)
1
100s 1ms 10ms
0.1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
100ms
ID , DRAIN CURRENT (A)
4
1
VGS = 5V VGS = 4V
0.01
TJ = MAX RATED 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
DC 0 100 0
10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. OUTPUT CHARACTERISTICS
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IRFD110 Typical Performance Curves
5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V
Unless Otherwise Specified (Continued)
VGS = 9V VGS = 8V VGS = 7V
ID(ON) , ON-STATE DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
4
5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX 4
TJ = -55oC
TJ = 25oC 3 TJ = 125oC 2
3 VGS = 6V 2
1
VGS = 5V VGS = 4V
1
0
0 5 0 2 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V)
0
1
2
3
4
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
2.0
NORMALIZED DRAIN TO SOURCE ON RESISTANCE
2s PULSE TEST DUTY CYCLE = 0.5% MAX
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 0.8A
rDS(ON) , DRAIN TO SOURCE ON RESISTANCE ()
2.0
1.5
1.5
1.0
VGS = 10V
1.0
0.5
VGS = 20V
0.5
0 0 2 4 ID , DRAIN CURRENT (A) 6 8
0 -60
-40
-20 40 0 20 60 80 100 TJ , JUNCTION TEMPERATURE (oC)
120
140
NOTE: Heating effect of 2s pulse is minimal. FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.15 C, CAPACITANCE (pF)
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
400
1.05
300
0.95
200 CISS 100 COSS CRSS
0.85
0.75 -60
-40
-20
0
20
40
60
80
100
120 140
0
0
10
TJ , JUNCTION TEMPERATURE (oC)
40 30 20 VDS , DRAIN TO SOURCE VOLTAGE (V)
50
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
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IRFD110 Typical Performance Curves
4.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = -55oC TJ = 25oC 2.4 TJ = 125oC
Unless Otherwise Specified (Continued)
10 ISD , SOURCE TO DRAIN CURRENT (A) 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
gfs , TRANSCONDUCTANCE (S)
3.2
2 TJ = 150oC 1.0 5 TJ = 25oC
1.5
0.8
2 0.1 0 0.2 0.4 1.2 0.6 0.8 1.0 1.4 1.6 VSD , SOURCE TO DRAIN VOLTAGE (V) 1.8 2.0
0 0 1 2 3 4 5 ID , DRAIN CURRENT (A)
FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE
20 ID = 1A VGS , GATE TO SOURCE (V) VDS = 20V VDS = 50V VDS = 80V 10
15
5
0 0 2 4 6 QG, GATE CHARGE (nC) 8 10
FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
-
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
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IRFD110 Test Circuits and Waveforms
(Continued)
tON td(ON) tr RL VDS
+
tOFF td(OFF) tf 90%
90%
RG DUT
-
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k 0.3F
G
DUT 0
Ig(REF) 0 IG CURRENT SAMPLING RESISTOR
S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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